Tunneling currents through ultra thin HfO_2/Al_2O_3/HfO_2 triple layer gate dielectrics for advanced MIS devices

摘要

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al_2O_3, Y_2O_3, La_2O_3, Ta_2O_5, TiO_2, ZrO_2 and HfO_2. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density-gate voltage (J_g-V_g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO_2/Al_2O_3/HfO_2 structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.