Braun's Multipliers: Spartan-3AN based Design and Implementation

摘要

Problem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The Field Programmable Gate Arrays (FPGAs) was currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The Sparatn-3An FPGA resources utilization for 4×4, 6×6, 8×8 and 12×12 bit Braun's multipliers were obtained and Analysis Of Variance (ANOVA) presented that the 12x12 multiplier had significant difference than other three multipliers. The mean delay time for four multipliers showed that as the size of multiplier increases the mean delay time also increases. Conclusion: In essence, parallel multipliers based on the FPGA technology can provide better solution for DSP processor, medical imaging and multimedia.