Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications

摘要

Neural networks are mimetic with biological neuron which are employed on digital computers. These networks are designed with CMOS technology using 0.45 mu m in cadence virtuoso. The scaling of CMOS limits parameters like power consumption, area and parallelism. To overcome the limitations, a nanoscale, nonvolatile Memristor device is used to design the synapses. The proposed network is designed for neuron synapse networks implemented with a memristor device. This network is compared with neuron linked with CMOS synapse. The proposed network has low power consumption, high spike frequency, and low delay value. The spike frequency of Memristor synapse increases by 65.51% when compared with the existing CMOS synapse and power consumption is reduced to 52.79%. The delay is reduced to 0.294 mu s. The simulation results are carried using Specter.