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机译:一种基于面积的高吞吐量基于移位的LDPC解码器的设计
Department of Electrical Engineering,National Chung Hsing University,Taichung 402, Taiwan ,Department of Electronic Engineering,Hsiuping University of Science Technology,Taichung 412, Taiwan;
Department of Electrical Engineering,National Chung Hsing University,Taichung 402, Taiwan;
Department of Electrical Engineering,National Chung Hsing University,Taichung 402, Taiwan;
Department of Electrical Engineering,National Chung Hsing University,Taichung 402, Taiwan;
Low-density parity-check codes; VLSI decoder architectures; shift-based LDPC decoder;
机译:用于5G LDPC代码的高性能和面积高效解码器的设计
机译:高通量多标准卷积Turbo解码的高效区域可扩展MAP处理器设计
机译:具有TDMP调度的高通量QC-LDPC解码器的设计
机译:高吞吐量LDPC解码的高效解码器设计
机译:适用于5G无线的高吞吐量FPGA QC-1DPC解码器架构。
机译:分层最小和迭代构建的一个区域高效和高吞吐量的后验概率LDPC解码器
机译:基于FPGA的随机LDPC解码器的减少延迟和区域有效架构