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Internal stresses and resistivity of low‐voltage sputtered tungsten films

机译:低压溅射钨膜的内应力和电阻率

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The continuing development of microelectronic circuits toward greater complexity has stimulated interest in new materials and processes compatible with the currently known silicon device technology. Tungsten has been considered as the first‐level conductor for a multilevel structure due to its relatively low electrical resistivity, its thermal expansion coefficient which matches fairly well to that of silicon, its demonstrated good adherence to the dielectrics of interest, and its ability to withstand high‐temperature processing. The present work is a part of a study of the dependence of the properties of low‐voltage triode sputtered tungsten films upon deposition parameters. The effects on internal stress and resistivity of tungsten films are reported here. Tungsten films have been deposited with thicknesses from 1000 to 15000 Å and with resistivities as low as 8 μω cm (1.55 of the bulk). These films were deposited at 1 μ argon pressure at rates in the range of 50–400 Å/min. The electrical resistivity was observed to increase with increasing deposition rate, decreasing film thickness, and decreasing substrate temperature. The impurity concentration was found to be small by electron microprobe and ion probe techniques and, hence, did not completely account for the observed changes in resistivity. The internal stress was determined by two x‐ray methods: (i) precision lattice parameter determination and (ii) a two‐exposure technique. In general, depending upon the deposition conditions, tensile or compressive stresses of the order 109-1010 dyn/cm2 were observed. The compressive stress was observed to increase with decreasing film thickness and increasing deposition rate. Increasing the substrate temperature caused the compressive stress to decrease to zero and become tensile. This changeover temperature was observed to be 650°C for a 5000‐&#-nxc5; film deposited at 115 Å/min. The observed results are discussed briefly in terms of microstructure changes.
机译:微电子电路朝着更高的复杂性的不断发展激发了人们对与当前已知的硅器件技术兼容的新材料和工艺的兴趣。钨由于其相对较低的电阻率,与硅相当的热膨胀系数,对感兴趣的电介质具有良好的粘附性以及承受能力而被认为是多层结构的第一级导体高温处理。目前的工作是研究低压三极管溅射钨膜的性能与沉积参数之间关系的一部分。本文报道了钨膜对内应力和电阻率的影响。沉积的钨膜厚度为1000到15000Å,电阻率低至8μωcm(占体积的1.55)。这些膜以1 µg氩气压力以50–400Å/ min的速率沉积。观察到电阻率随沉积速率的增加,膜厚度的减小和基板温度的降低而增加。通过电子探针和离子探针技术发现杂质浓度很小,因此并不能完全解决所观察到的电阻率变化。内部应力通过两种X射线方法确定:(i)精确晶格参数确定和(ii)两次曝光技术。通常,根据沉积条件,观察到的拉应力或压应力约为109-1010 dyn / cm2。观察到压应力随着膜厚度的减小和沉积速率的增加而增加。基板温度的升高导致压应力降至零并变为拉伸。对于5000-&#-nxc5,该转换温度为650°C;膜以115Å/ min的速度沉积。观察结果就微观结构变化进行了简要讨论。

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    《Journal of Applied Physics 》 |1973年第3期| 共8页
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  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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