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Experimental and theoretical study of capacitive memory of metal-oxide-semiconductor devices based on Er-doped In_2O_3 nano-column arrays

机译:基于ER-掺杂IN_2O_3纳米柱阵列的金属氧化物半导体器件电容存储器的实验与理论研究

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摘要

The enhanced electronic memory performance of glancing angle deposited erbium-doped indium oxide (In_2O_3∶Er) transparent nano-column (NCol) based metal-oxide-semiconductor (MOS) structured memory devices is reported. The fabricated MOS devices are Au/ In_2O_3/p-Si, Au/0.26 at. % In_2O_3∶Er/p-Si, and Au/0.48 at. % In_2O_3∶Er/p-Si. The capacitance-voltage (C-V), conductance-voltage (G-V), C-V hysteresis, endurance, and retention properties from the cyclic current-voltage (I-V) curve of the fabricated devices were investigated in detail. The overall interface state density (D_(it)) for the devices at the different applied frequency (f) decreases with the increase in Er doping. The observations obtained from C-V, G-V, and D_(it)-f curves were theoretically explained considering a modified delta depletion model. It was found that Au/0.48 at. % In_2O_3∶Er/p-Si does not go to inversion even at a high applied voltage. The constant capacitive memory window (MW) for Au/In_2O_3/p-Si is ~1 V at the depletion region. MW increases from ~0.6V (sweep voltage ±6V) to ~2.5 V (sweep voltage ±16 V) and ~1.4V (sweep voltage ±6V) to ~6.8 V (sweep voltage ±16 V), respectively, for Au/0.26 at. % In_2O_3∶Er/p-Si and Au/ 0.48 at. % In_2O_3∶Er/p-Si. The increased MWs despite reduced D_(it) is explained in detail by primarily considering increased polarization switching of the In-O-Er material, asymmetric charge injection from the top electrode, and the presence of the oxygen-rich environment. The I-V hysteresis performance of the devices under a reverse bias was also improved with Er doping due to the migration of O~(2-) inside the oxide layer. The whole analysis indicates that the gate-controlled Au/0.48 at. % In_2O_3∶Er/p-Si MOS device is appropriate for capacitive memory applications.
机译:报道了增强的透镜掺杂掺铒氧化铟(IN_2O_3: er)透明纳米柱(NCOL)的金属氧化物半导体(MOS)结构存储器件的增强的电子存储器性能。制造的MOS装置是Au / In_2O_3 / p-Si,Au / 0.26。 %In_2O_3: er / p-si,和au / 0.48。 %in_2o_3: er / p-si。研究了来自制造装置的循环电流 - 电压(I-V)曲线的电容电压(C-V),电导 - 电压(G-V),C-V滞后,耐久性和保持性。不同施加频率(F)的设备的整体接口状态密度(D_(IT))随着ER掺杂的增加而降低。考虑到改进的ΔFepletion模型理论上解释了从C-V,G-V和D_(IT)-F曲线获得的观察结果。发现AU / 0.48 AT。即使在高施加的电压下,%IN_2O_3:2ER / P-SI也不会转换为反转。用于Au / In_2O_3 / p-Si的恒电容存储器窗口(MW)在耗尽区域处是〜1V。 MW从〜0.6V(扫描电压±6V)增加到〜2.5V(扫描电压±16V),〜1.4V(扫描电压±6V)分别为Au / / 0.26 at。 %IN_2O_3: er / p-si和au / 0.48。 %in_2o_3: er / p-si。尽管减少了D_(IT),但通过主要考虑从顶部电极的偏振切换,从顶部电极的不对称电荷注入的偏振切换以及富氧的环境的存在,详细解释了D_(IT)的增加。由于氧化物层内部的O〜(2-)迁移,在反向偏压下,逆偏压下的装置的I-V滞后性能也随着O〜(2-)的迁移而改善。整体分析表明栅极控制的AU / 0.48 AT。 %IN_2O_3:2ER / P-SI MOS设备适用于电容存储器应用。

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  • 来源
    《Journal of Applied Physics》 |2020年第9期|095704.1-095704.13|共13页
  • 作者单位

    Department of Physics National Institute of Technology Durgapur Durgapur 713209 India;

    Department of Electronics and Communication Engineering National Institute of Technology Nagaland Dimapur 797103 Nagaland India;

    Department of Physics National Institute of Technology Durgapur Durgapur 713209 India;

    Department of Physics National Institute of Technology Durgapur Durgapur 713209 India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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  • 正文语种 eng
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