High-Performance Mixed PRML Architecture for Optical Data Storage System

摘要

A new mixed analog/digital partial response maximum likelihood (PRML) architecture for the optical drive system is presented. To realize a high-speed, low-power and low-cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits for providing high-speed and low-power data detection for optical data storage systems. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and reduced area by 42%, therefore it provides a high-speed, low-power and low-cost system on chip solution for the future optical drive system. A test chip produced is fabricated using 0.18 μm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.