Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space

摘要

VLSI-implementations are often applied to solve the high computational cost of pattern matching but have usually low flexibility for satisfying different target applications. In this paper, a digital word-parallel associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern recognition, is reported applying the squared Euclidean distance measure. The reported architecture features reconfigurable parallelism, dual-storage space to achieve a flexible number of reference vectors, and a dedicated majority vote circuit. Programmable switching circuits, located between vector components, enable scalability of the searching parallelism by configuring the reference feature-vector dimensionality. A pipelined storage with dual static-random-access-memory (SRAM) cells for each unit and an intermediate winner control circuit are designed to extend the applicability by improving the flexibility of the reference storage. A test chip in 180nm CMOS technology, which has 32 rows, 4 elements in each row and 2-parallel 8-bit dual-components in each element, consumes altogether 61.4mW and in particular only 11.9mW during the reconfigurable KNN classification (at 45.58MHz and 1.8 V). (C) 2016 The Japan Society of Applied Physics