A Configuration Optimization Method for On-chip Two-level Cache Memory Based on Memory Access Sequence Analysis

摘要

Thanks to the recent progress of integration technology, it becomes possible to implement two level cache memory on the same chip with CPU core, peripheral circuits and so on. In this memory system, the average memory access time can vary depending on the cache con- figuration such as the size of primary and secondary cashes, block sizes and associativity. In this research, an average access time estimation method for on-chip two level cache memory with full associative configuration is proposed. The proposed method is based on the analysis of memory ascess sequence. FI.om the experimental results, the proposed method can decide the optimal configuration of on-chip memory more than hundred times faster than the conventional method based on a time-consuming repetitive simulation dose.