Processor Generation Method for Pipelined Processors in Consideration with Pipeline Hazards

摘要

In this paper, a synthesizable HDL generation method for pipelined processors which includes multi-cycle operation, delayed branch and external interruption from clock based micro- operation description of instructions. The data path structure and control logic of the processor are generated by applying a processor model which includes hardware interlock, delayed branch and external interrupt control logic to micro-operation description. Then, (1) data path structure, (2) hardware interlock logic for multi-cycle operation, (3) branch control logic and (4) interrupt control logic are generated. Easiness of large design space exploration and effectiveness of the method was evaluated through experiments using a subset of MIPS R3000 instruction set.