Design, implementation and verification through a real-time test-bed of a multi-rate CDMA adaptive interference mitigation receiver for satellite communication

摘要

This paper presents the design, the implementation, and the main performance results of a multi-rate code division multiple access (CDMA) interference mitigation receiver for satellite communication. Such activity was performed within a research project supported by the European Space Agency (ESA), whose aim was to demonstrate the suitability of the linear adaptive interference mitigation detector (IMD) named extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for single-user detection of a CDMA signal in third-generation (3G) satellite networks. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in a blind mode, i.e. it only requires knowledge of the timing of the wanted user's signature code, and is therefore very well suited for integration into handheld user terminals. Experimental results in terms of bit error rate with respect to the theoretical behaviour were derived through a specifically developed test bed. Signal plus multiple access interference generation is performed via a computer-controlled arbitrary waveform generator, followed by frequency up-conversion to the standard intermediate frequency of 70 MHz. Additive white Gaussian noise is then injected with the aid of a precision noise generator. The core of the test bed is a flexible digital receiver prototype featuring the EC-BA1D detector plus all functions ancillary to IMD (multi-rate front-end, automatic gain control, code acquisition and tracking, carrier synchronization, etc.). Those functions were implemented through careful mixing of different technologies: field programmable gate arrays (FPGAs) for computing-intensive signal processing functions, digital signal processor (DSP) for housekeeping and monitoring, and application specific integrated circuit (ASIC) for adaptive IMD. The adopted design flow also allows an easy re-use of the prototype architecture to come to an overall integration of the receiver into a single ASIC with modest complexity and power consumption increase with respect to a conventional detector.