Area and time trade-offs for iterative modular division over GF(2~m): novel algorithm and implementations on FPGA

摘要

Public key cryptography is a concept used by many useful functionalities, such as digital signature, encryption, key agreements, etc. For those needs, elliptic curve cryptography is an attractive solution. Cryptosystems based on elliptic curves (EC) need a costly modular division. Efficient implementations of this operation are useful for both area-constrained designs working in affine coordinates and high-speed processors. For that purpose, this work highlights the most efficient iterative modular division algorithm and explores different time and area trade-offs on FPGA. In particular, a novel algorithm is proposed and a specific feature of the algorithm is exploited. To show the impact of the different trade-offs on a whole architecture, dividers are also integrated in a low-footprint ECC processor. To the best of our knowledge, it is the first report about an iterative digit-serial modular division algorithm, the first area and time tradeoff analysis of an iterative algorithm and the best result among the very few implementations on FPGA.