A 3.4-Gbps clock and data recovery circuit with a forwarded clock in a 0.13-μm CMOS technology

摘要

A clock and data recovery (CDR) circuit has been developed for a clock-forwarded 3.4-Gbps serial link. The loss of the signal channel is compensated by a linear equaliser whose output is applied to eight samplers which provides edge- and data-samples of the serial data input. Based on the edge- and data-samples, the phase of a voltage-controlled oscillator (VCO) running at one-fourth of the data rate is adjusted to get the optimum eight-phase sampling clocks. Implemented in a 0.13-μm standard CMOS process, the CDR circuit shows the bit-error rate (BER) less than 10~(-15).