A Comprehensive Analysis of Design and Simulation of Area Efficient CRC Algorithm for ZIGBEE Application

摘要

In this paper, the design of area efficient ZigBee Digital Transmitter is proposed. Several researchers have designed the ZigBee transmitter using a Matlab or Simuhnk, a Schematic and also using VHDL which implemented through Spartan and Virtex FPGA family. The Digital Transmitter is designed using Verilog, which uses less number of slices, LUTs, etc. The paper is aimed in designing ZigBee transmitter for PHY & MAC layer of IEEE 802.15.4 standard using Verilog is to be analyzed with the simulated results which are obtained through Xilinx in order to reduce the cost and complexity. During the process, both the physical and MAC layers are studied and configured accordingly to the power constraints and surrounding environment. The evaluation of simulation mainly confirms in fixing the errors. The error detection techniques which are most commonly used are redundancy check, checksum, longitudinal redundancy check, and cyclic redundancy check which are done during the proposed research work. Using the CRC the proposed work attempts to detect 99.99% errors during transmission. The block check sequence uses the 16 bit width in CRC-16 to generate the continuous binary number with the data stream. The 20% of reduced area is achieved for proposed system when compared to existing system.