Toward a spoof-tolerant PMU network architecture

摘要

Formulation of and solution to an architecture design/upgrade problem for a PMU network overlaid on a transmission circuit are presented. The design/upgrade aims to cost-effectively enhance the phasor observability of the transmission circuit in the face of GPS signal spoofing attacks on the PMU network. Synchrophasor availability, defined at each bus as the fraction of time on average its voltage synchrophasor is correctly present for real-time usage, now takes into account of possible altered phasor data caused by spoofing, in addition to loss of PMU data caused by communication interruptions considered in our previous work. Achieved synchrophasor availability profiles of a PMU network constructed with and without imposing a spoofing-tolerant criterion for the 68-bus test system are compared to reveal the cost and benefit of spoofing-tolerance. The tolerance sought is achieved through two new developments. (1) Stochastic models for computing synchrophasor availability as a part of the network design/upgrade algorithm now include event arrival rates associated with spoofing induced data alteration and data recovery at every PMU node. (2) A practicable and scalable real-time isolation scheme is proposed using detection consensus of the neighboring partitions of a suspected PMU in a normally observable transmission circuit. Upon isolation of a spoofed PMU, its real-time function is accommodated through inference using analytic redundancy provided by a partial circuit model bordered by some intact neighboring PMUs. Detection, isolation, and inference are tested on the 68-bus system and shown guaranteed success for any single spoofed PMUs. Though promising test results are observed for simultaneous spoofing attacks on multiple PMUs, more cost-effective isolation and inference schemes are desirable.