POWER-AWARE MULTI-LEVEL AND-XOR NETWORK SYNTHESIS

摘要

Logic minimization based on AND-OR decomposition of functions is a well-studied area. However, minimization, particularly power-aware technique, based on AND-XOR decomposition has received relatively lesser attention. This paper presents a multi-level AND-XOR network synthesizer that incorporates area-power trade-off in the decision-making process. The synthesizer can produce circuits consuming 23.77% less switching power and 9.53% less leakage power, on an average, over synthesis approaches targeting area minimization.