Code transformations to prevent timing anomalies

摘要

Divide-and-conquer approaches to worst-case execution-time analysis (WCET analysis) pose a safety risk when applied to code for complex modern processors: interferences between the hardware acceleration mechanisms of these processors lead to timing anomalies, i.e., a local timing change causes an either larger or inverse change of the global timing. This phenomenon may result in dangerous WCET underestimation. This paper presents results of our work on strategies for eliminating timing anomalies. These strategies are purely based on the modification of software, i.e., they do not require any changes to hardware. In order to eliminate the timing anomalies originating from the processor's out-of-order instruction pipeline, we explore different methods of inserting instructions in the program code that eliminate all but one alternative schedules for the dynamic instruction scheduler. We also present a software-only way to force predictability for a two bit saturating counter branch predictor.