A study of decimal left shifters for binary numbers

摘要

The importance of decimal floating-point (DFP) arithmetic has been growing in the last years, and specifications for it are included in the revised IEEE 754 Standard for Floatingpoint Arithmetic (IEEE 754-2008). IEEE 754-2008 specifies a binary encoding for decimal significands, in which the significands of DFP numbers are represented as unsigned binary integers. For this representation, which is commonly referred to as the binary integer decimal (BID) encoding, fast decimal left shifting of a binary number is useful for operand alignment, normalization, overflow avoidance, and quantize operations. A decimal left shift of an unsigned binary integer, I, by S digit positions corresponds to multiplying I by 10~S. This paper presents the theory and design of decimal left shifters for binary numbers. The designs perform decimal left shifting using optimized constant multiplications by selected powers of ten. We propose and analyze different combinational and sequential decimal left shifter architectures for binary numbers. The designs are compared to one another in terms of area and delay using both theoretical estimates and synthesis results for 16-digit (54-bit) binary inputs and 4-bit shift amounts. The results indicate that an optimized radix-2 decimal shifter implementing partial shifters in carry-save format has 80% less area and 68% less delay than a lookup table followed by a binary multiplier to compute 1 × 10~S, when both designs are optimized for delay. When both designs are optimized for area, the radix-2 decimal shifter has 89% less area and 31% less delay.