An Improved Delayed Signal Cancellation PLL for Fast Grid Synchronization Under Distorted and Unbalanced Grid Condition

摘要

Cascasded delayed signal cancellation (DSC) phase-locked loop (PLL) technique has been attractive for grid synchronization under nonideal grid voltage due to its good harmonics filtering capability. However, it has to face the challenge of slow dynamic response. In this paper, an improved DSC-PLL that features high filtering capability, fast dynamic response and simple structure is presented. This PLL employs only one DSC block and one moving average filter (MAF) block to eliminate all even-order and odd-order harmonics while a second-order phase lead compensator and q-axis feedforward path are introduced to increase the PLL bandwidth. The effect of the phase lead compensator on PLL dynamic performance is analyzed. The feedforward path works only when grid voltage frequency or phase jumps and will not affect the steady state behaviors. Therefore, the PLL can improve the phase estimation accuracy and dynamic speed at the same time even under highly distorted and unbalanced grid voltage. Moreover, linear Lagrange interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. The effectiveness of the proposed method is validated by both simulation and experimental results. The comparison results with the existing cascaded DSC-PLL and standard MAF-PLL are also presented.