Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems

摘要

A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.