机译:基于硬件软件与ModelSim协同设计的电路架构测试验证
Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103 USA,School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada;
School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada;
School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada;
School of Engineering and Physics, Faculty of Science and Technology, University of the South Pacific, Suva, Fiji;
School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada;
School of Engineering and Computer Science,Independent University, Dacca 1329, Bangladesh;
Built-in self-test; Embedded cores-based system-on-chips; Fault injection; Fault simulation; Module under test; Test pattern generator; Verilog hardware description language;
机译:基于依赖图的验证和具有SAT相关公式的硬件/软件协同设计的综合。
机译:基于系统依赖图的系统级软硬件协同设计与验证方法
机译:硬件和软件协同设计:基于无缓冲数据流的片上网络交换机的体系结构建议
机译:基于脚本的循环真实验证框架,用于加速硬件和软件共同设计的系统开发的risc-v架构
机译:基于核的数字电路的空间压缩中的硬件和软件协同设计。
机译:基于分形特征的跌倒检测系统软硬件协同设计
机译:一个系统级硬件/软件协同设计和与自定义硬件的商品多处理器系统的协同验证案例