Resolving Load Data Dependency Using Tunneling-Load Technique

摘要

The new technique for reducing the load latency is presented. This technique, named tunneling-load, utilizes the register specifier buffer in order to reduce the load latency with- out fetching the data cache speculatively, and thus eliminates the drawback of any load address prediction techniques. As a con- sequence of the trend toward increasing clock frequency, the in- ternal cache is no longer able to fill the speed gap between the processor and the external memory, and the data cache latency degrades the processor performance. In order to hide this la- tency, several techniques predicting the load address have been proposed.