Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of -Order Issue Processors

摘要

This paper presents a new approach to the pre- cise interrupt handling problem in modern processors with mul- tiple out-of-order issues. It is difficult to implement a precise in- terrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt oc- curs. In addition, the scheme removes all the associative search- ing operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off be- tween high performance and low complexity.