机译:嵌入式处理器的高效泄漏数据TLB设计
The authors are with the Faculty of Science and Technology,Keio University, Yokohama-shi, 223-0061 Japan;
The authors are with the Faculty of Science and Technology,Keio University, Yokohama-shi, 223-0061 Japan;
The authors are with the Faculty of Science and Technology,Keio University, Yokohama-shi, 223-0061 Japan;
The authors are with the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology,Koganei-shi, 184-8588 Japan;
The authors are with the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology,Koganei-shi, 184-8588 Japan;
The authors are with the Faculty of Science and Technology,Keio University, Yokohama-shi, 223-0061 Japan;
leakage power; TLB; embedded processor;
机译:嵌入式处理器泄漏有效数据TLB设计
机译:嵌入式处理器的高效泄漏指令TLB设计
机译:嵌入式处理器的高效泄漏指令TLB设计
机译:减少嵌入式处理器指令TLB的泄漏功耗
机译:一个有效的设计空间探索框架,用于优化省电的异构多核多线程嵌入式处理器体系结构。
机译:基于面向嵌入式图像处理的FPGA的高效智能CMOS相机
机译:节能嵌入式系统的多线程处理器设计