机译:适用于多核架构的可扩展高速缓存优化的并发FIFO队列
School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea;
Software Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Korea;
Software Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Korea;
School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea;
FIFO queue; multicore processor; cache-line contention; compare-and-swap; fetch-and-store;
机译:适用于多核架构的可扩展高速缓存优化的并发FIFO队列
机译:可扩展,便携式且内存有效的无锁FIFO队列
机译:集成无锁和组合技术以实现实用且可扩展的FIFO队列
机译:并发FIFO队列的性能,可伸缩性和语义
机译:许多核心架构上并发优先级队列的模型
机译:使用无锁并发的可扩展多核运动计划
机译:并发FIFO队列的性能,可伸缩性和语义