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首页> 外文期刊>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences >A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm
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A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

机译:基于扩展欧几里得算法的模块化乘法/除法硬件算法

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摘要

A hardware algorithm for modular multiplication/division which performs modular division, Montgomery multiplication, and ordinary modular multiplication is proposed. The modular division in our algorithm is based on the extended Euclidean algorithm. We employ our newly proposed computation method that consists of processing the multiplier from the most significant digit first to calculate Montgomery multiplication. Finally, the ordinary modular multiplication is based on shift-and-add multiplication. Each of these three operations is carried out through the iteration of simple operations such as shifts and additions/subtractions. To avoid carry propagation in all additions and subtractions, the radix-2 signed-digit representation is employed. A modular multiplier/divider based on the algorithm has a linear array structure with a bit-slice feature and carries out n-bit modular multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n. This multiplier/divider can be implemented using a hardware amount only slightly larger than that of the modular divider.
机译:提出了一种用于模块化乘法/除法的硬件算法,该算法执行模块化除法,蒙哥马利乘法和普通模块化乘法。我们算法中的模除法基于扩展的欧几里得算法。我们采用了我们新提出的计算方法,该方法包括先从最高有效位开始处理乘法器以计算蒙哥马利乘法。最后,普通的模块化乘法是基于移位加法乘法的。这三个操作中的每一个都是通过简单操作(例如移位和加法/减法)的迭代来执行的。为避免所有加法和减法中的进位传播,采用了基数为2的带符号位表示。基于该算法的模块化乘法器/除法器具有带位切片功能的线性阵列结构,并在O(n)个时钟周期内执行n位模块化乘法/除法,其中时钟周期的长度是恒定的并且与。该乘法器/除法器可以使用仅比模块化除法器大一些的硬件来实现。

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