首页> 外文期刊>IEICE Transactions on Electronics >A Second-order Multibit Complex Bandpass ΔΣad Modulator With I, Q Dynamic Matching And Dwa Algorithm
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A Second-order Multibit Complex Bandpass ΔΣad Modulator With I, Q Dynamic Matching And Dwa Algorithm

机译:具有I,Q动态匹配和Dwa算法的二阶多位复带通ΔΣad调制器

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We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for 1 and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18μm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20MS/S with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm~2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.
机译:我们已经设计,制造和测量了二阶多位开关电容器复数带通ΔΣAD调制器,以评估我们的新算法和体系结构。我们提出了一种具有I,Q动态匹配的前向路径中的复杂带通滤波器的新结构,该结构与传统的等效,但可以分为两个独立的部分。结果,采用我们提出的复合滤波器的ΔΣ调制器也可以分为两个独立的部分,并且在由复合滤波器和反馈DAC形成的上下路径之间没有信号线交叉。因此,可以简化调制器的布局设计。通过添加多路复用器,调制器中的两组信号路径和电路在I和Q之间改变,而CLK在高和低之间改变。对称电路在特定时间段内用于1和Q路径,并且在另一时间段内通过多路复用器切换到用于Q和I路径的对称电路。以这种方式,减少了I和Q路径之间的失配的影响。调制器中使用了两个九级量化器和四个DAC,以实现低功耗和较高的信噪比和失真度(SNDR),但是DAC的非线性不是噪声形状,ΔΣAD调制器的SNDR降级。我们还采用了一种新的复杂带通数据加权平均(DWA)算法,以抑制复杂形式的多位DAC的非线性效应,以实现高精度;只需添加简单的数字电路即可实现。为了评估这些算法和体系结构,我们实现了使用0.18μmCMOS技术的调制器,可在2.8 V电源下工作;在20MS / S时,它的实测峰值SNDR为64.5 dB,信号带宽为78 kHz,耗散28.4 mW,占用芯片面积为1.82 mm〜2。这些实验结果证明了以上两种算法的有效性,并且该算法可以扩展到其他复杂的带通ΔΣAD调制器,以应用于无线通信系统中的低中频接收机。

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