TEGチップを用いたオープン故障の解析

摘要

The high integration of the semiconductor technology advances, and the fault detection and the failure diagnosis of LSI become difficult. Especially, a practicable modeling of an open fault has not been performed yet, though measures against the open fault become important more with advancement of LSI process technology. So, we have fabricated TEG (Test Element Group) chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, the measurement data of the TEG chip is analyzed, and we report how influence a logical value of a faulty signal line with full open defect actually depend on those of the adjacent signal lines in the real chip.%半導体技術の高集積化が進みLSIの故障検出や故障診断が難しくなってきている．特に，オープン故　障への対策はLSIの微細化に伴いますます重要となってきているが，オープン故障の実用的なモデル化はいまだなされていない．そこで，我々はオープン故障を組み込んだTEG（Test Element Group）チップを作製し，その測定データに基づいたオープン故障のモデル化に取り組んでいる．本研究では，TEGチップの測定データの解析を行い，実チップ中の近接する信号線がオープン故障の信号線に実際にどのような影響を及ぼしているかについて報告する．