遅延観測方式によるチップ内電源ノイズの観測

摘要

To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measuring on-chip voltage waveforms. To overcome the trade-off in the voltage resolution and the measurable frequency band, we designed inverter chain circuits that have the different lengths of series inverters: the short chain provides the high frequency and the low resolution, while the long chain provides the low frequency and the high resolution. We measured the on-chip noise waveforms using a 90-nm CMOS test chip with a 50-inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the synchronized inverter group, although resonance frequencies are virtually the same - 160 MHz - when the activating ratios change.%給電系設計のためのチップ内電源ノイズ評価手法として，インバータ回路の電位変動を出力波形の遅延変動量に変換し外部でこれを観測するノイズ波形評価手法を開発した．本手法では、段数切替可能な多段インバータ回路を用いることで，インバータ段数変更に伴なう電圧分解能と観測可能な周波数帯域のトレードオフを解消した．90nm CMOSテクノロジーを用いて本測定手法に基づくテストチップを開発し，50段インバータ回路では320μm~2の小サイズながら電圧分解能1mV，時間分解能20psを実現し，周波数160MHzのチップーパッケージ共振に由来するチップ内部の電源ノイズ波形の観測に成功した．