Evaluation of a Multicore Reconfigurable Architecture

摘要

A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection network is introduced. A comparision of a tile-based architecture and the proposed multicore architecture in terms of performance is examined. Then, an evaluation with different core sizes is implemented in order to find out how the size of cores in a homogeneous system influences on the performance and the internal fragmentation of target applications. Using real applications implemented on the proposed architecture in which cores are based on NEC Electronics' DRP-1, the evaluation result shows that the size of core is a trade-off between throughput and resource usage, and the size of two or three DRP tiles is an appropriate choice for many cases.