TFT SRAMを用いた3D-FPGAの開発

摘要

1. 本発表の3D-FPGAのコンセプトはconfiguration SRAMをCMOS配線上にTFTで形成することである。2. 3D-FPGAは従来のFPGAにおいてチップの数10％を占めるconfiguration SRAMを三次元方向に移すことにより大幅にChip面積を小さくすることができ、それに伴いパワー・コスト・性能が改善する。%Monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor lon/loff ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.