最大フロー最小カット定理を用いた不揮発レジスタの書込み削減

摘要

Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attention. Such devices can integrate in CMOS LSI and can keep the data when power off with very small overhead for recovering the data when power on. By using such devices, we can apply fine and low overhead power control for CMOS LSI. The write energy of such devices, however, is a little bit large (about 3-10 times) compared with that of a usual D flip-flop, and some type of such devices have the limitation of the total number of writes. So it is very important to control the write operations on such devices. In the research, a write reduction method for non-volatile registers is proposed based on the min-cut max-flow theorem. The smallest cut-set from the point of the switching activity is searched and non-volatile registers are injected to the cut-set independent from the original register position. The method has been implemented and applied to ISCAS 89 benchmarks. 6 circuits in 11 benchmarks showed the write reduction more than 3％. 4.9％〜34.6％ write reductions (20.8％ on average) have been found when the non-volatile registers are written at every clock, and 3.8％〜34.8％ write reductions (16.6％ on average) have been found when the non-volatile registers are written at regular intervals.%近年，磁気トンネル結合を用いた次世代不揮発メモリ/レジスタが注目されている.これらはCMOS素子と集積可能で，電源遮断時でも記憶を保持でき，電源を戻す時のオーバーヘッドが少ないので，細かい粒度でLSIの電源管理が可能となる.しかし，不揮発レジスタは通常のレジスタに比べて書込み電力が3-10倍程度大きく，かつ書込み回数に制限があるものもあり，不要な書込みを制限することが必要不可欠である.そこで本稿では，最大フロー最小カツト定理を用いた不揮発レジスタの書込み回数削減手法を示す.本手法では，元のレジスタの位置と無関係に，回路中の信号のスイッチング確率の総和が最小となるカツトセットを探索し，そこに値保持用の不揮発レジスタを挿入する.本手法をISCAS 89ベンチマーク回路に適用したところ，元のレジスタの場所に入れるのと比較して，11回路中6個の回路で3％以上の削減が認められ，毎クロック書込みの場合で4.9％〜34.6％(平均で20.8％),一定間隔を置いて書き込む場合で3.8％〜34,8％(平均で16.6％)の削減が得られることを示した.