Application-specific architecture for fast transforms based on the successive doubling method

摘要

The successive doubling method is an efficient procedure for the design of fast algorithms for orthogonal transforms of length N=r/sup n/, where the radix r is a power of 2. A partitioned systolic architecture is presented for the two standard radix successive doubling algorithms: decimation in time (DIT) and decimation in frequency (DIF). The index space of the data is projected onto the index space associated with a column of processors, interconnected using a perfect unshuffle (DIT) or shuffle (DIF) interconnection network, defined by permutations of the order log/sub 2/r. The result is a partitioned systolic array with Q processors (Q=r/sup i/, 0>or=i>n), which extracts the maximum spatial and temporal parallelism achieved by the successive doubling algorithm and can be integrated in VLSI and WSI technologies.