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Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes

机译:系统短块码的高效最大似然软解码器设计

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Maximum likelihood soft-decision decoding of linear block codes is addressed in this correspondence. A novel algorithm based on Chase-2 algorithm for the decoding of systematic binary block codes is detailed. A double re-encoding technique in place of the classical algebraic decoding for the computation of the candidate codeword list is the major innovation of the proposed algorithm. This approach has been successfully applied to systematic block codes that have a code rate equal to 1/2 and a parity check matrix composed of an invertible submatrix for the redundancy part. Simulation results show performance close to the optimum maximum likelihood decoding for an excellent tradeoff between BER performance and computational complexity. Then, the challenging issue of designing a decoder for a specific family of short binary block codes, called Cortex codes is also described. Three soft decoders for Cortex codes with lengths equal to 32, 64, and 128 and a code rate equal to 1/2 have been designed. Then, all the decoders were successively implemented onto an field-programmable gate array (FPGA) device. To our knowledge, they are the first efficient digital implementations of Cortex codes.
机译:以此方式解决线性分组码的最大似然软判决解码问题。详细介绍了一种基于Chase-2算法的系统二进制块码解码算法。替代经典代数解码的双重重编码技术来计算候选码字列表是该算法的主要创新。此方法已成功应用于具有1/2编码率和冗余部分的由可逆子矩阵组成的奇偶校验矩阵的系统块代码。仿真结果表明,在BER性能和计算复杂度之间取得良好折衷的情况下,性能接近最佳最大似然解码。然后,还将描述为特定系列的短二进制块码(称为Cortex码)设计解码器的挑战性问题。已经设计了三种用于Cortex码的软解码器,其长度分别等于32、64和128,编码率等于1/2。然后,将所有解码器相继实现到现场可编程门阵列(FPGA)器件上。据我们所知,它们是Cortex代码的首批高效数字实现。

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