A Reduced Common-Mode-Voltage Pulsewidth Modulation Method With Output Harmonic Distortion Minimization for Three-Level Neutral-Point-Clamped Inverters

摘要

This article presents a carrier-based pulsewidth modulation (PWM) strategy to reduce the common-mode voltage (CMV) with output harmonic distortion minimization for three-level neutral-point-clamped (NPC) inverters. The proposed method is first presented for three-level NPC inverters, and then, generalized for odd n-level inverters including NPC and cascaded inverters. With the help of base voltage vectors, the odd n-level space vector diagram can be transformed into a two-level one on which the modulation analysis is conducted This strategy utilizes two zero CMV vectors and one virtual vector, which is the combination of two other vectors with equal duty-split cycle, thereby, reducing the CMV magnitude and suppressing low-frequency components of the CMV. The construction of space vector diagrams with virtual vectors leads to three switching sequences in which one switching sequence gives the best harmonic performance under the harmonic distortion analysis, thereby significantly reducing the output harmonic distortion. Therefore, the proposed reduced CMV PWM strategy achieves zero average CMV in one switching period, and minimized output harmonic distortion in comparison to the existing methods. Simulation and experimental results confirm the effectiveness of the proposed strategy.