The digital front-end electronics for the space-borne INTEGRAL-SPI experiment: ASIC design, design for test strategies and self-test facilities

摘要

The flight model of the digital front-end electronics (DFEE) of the gamma-ray spectrometer SPI has been recently integrated on the INTEGRAL satellite spacecraft. The processing core of the DFEE is based on a dedicated application specific integrated circuit (ASIC). We report on the unified design and test methodology that was deployed to cover the entire life cycle of this subsystem, from initial design simulation to operational self-test and diagnosis operations after launch. Strong emphasis is put on the ASIC design-for-test strategies, from very-high speed integrated circuit description language IEEE 1076 (VHDL) simulation and test bench validation to full scan fabrication test coverage and inflight self-test capability.