A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider

摘要

Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20$,times ,$20 ${mu}{rm m}^{2}$ pixels, laid out in an array of 64$,times ,$64 elements and was fabricated in a 3-tier 0.18 ${mu{rm m}}$ Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout.