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首页> 外文期刊>IEEE Transactions on Nuclear Science >A 1.6-Gsps High-Resolution Waveform Digitizer Based on a Time-Interleaved Technique
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A 1.6-Gsps High-Resolution Waveform Digitizer Based on a Time-Interleaved Technique

机译:基于时间交错技术的1.6 Gsps高分辨率波形数字化仪

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A high-speed and high-resolution Analog-to-Digital Conversion circuit is the crucial part in many physics experiments, data communication, and measurement instrumentation. We present the design and test results on a 1.6-Gsps high-resolution waveform digitizer based on a high-speed AD conversion and time-interleaved technique. Considering the mismatch (gain, offset, and skew) among different ADC channels, we employ real-time correction algorithms integrated in an FPGA to enhance the system performance. In the very high-speed situation, simplification of digital processing algorithms is an important task to guarantee a high processing speed. We proposed a novel correction method based on a fully parallel structure. To achieve good performance, we designed a special jitter-cleaning circuit for the sampling clock and front end coupling circuits for the ADCs, and carefully implemented the hardware circuits to guarantee the signal integrity. Test results indicate that this waveform digitizer achieves a sampling rate of 1.6 Gsps and an ENOB around 11 bits for an input signal from 5 MHz to 150 MHz. The ENOB is still above 10.4 bits for an input up to 300 MHz, with the correction algorithms applied.
机译:高速,高分辨率的模数转换电路是许多物理实验,数据通信和测量仪器中的关键部分。我们介绍了基于高速AD转换和时间交错技术的1.6 Gsps高分辨率波形数字化仪的设计和测试结果。考虑到不同ADC通道之间的失配(增益,偏移和偏斜),我们采用了集成在FPGA中的实时校正算法来增强系统性能。在非常高速的情况下,简化数字处理算法是保证高速处理的重要任务。我们提出了一种基于完全并行结构的新颖校正方法。为了获得良好的性能,我们为ADC的采样时钟和前端耦合电路设计了专用的抖动消除电路,并仔细实施了硬件电路以确保信号完整性。测试结果表明,对于5 MHz至150 MHz的输入信号,该波形数字化仪可实现1.6 Gsps的采样率和11位左右的ENOB。对于高达300 MHz的输入,ENOB仍高于10.4位,并应用了校正算法。

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