A 4-MHz, 256-Channel Readout ASIC for Column-Parallel CCDs With 78.7-dB Dynamic Range

摘要

A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm(2) and fabricated in 180-nm CMOS technology, achieves 22 e(-) equivalent noise charge (ENC) and a dynamic range of 190 ke(-) (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a 256 x 256 pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron.