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首页> 外文期刊>IEEE Transactions on Nuclear Science >Shunt Regulator for the Serial Powering of the ATLAS CMOS Pixel Detector Modules
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Shunt Regulator for the Serial Powering of the ATLAS CMOS Pixel Detector Modules

机译:用于ATLAS CMOS像素检测器模块串行供电的并联稳压器

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A shunt regulator was designed to meet the specifications for the serial powering of the CMOS pixel detector modules in compatibility with the next upgrade of the ATLAS detector. Serial powering greatly increases the system's power efficiency when compared to a parallel powering scheme and allows for significant material budget savings in the power cabling. In such a scheme, each pixel detector chip is powered by a shunt regulator that takes in a constant current and produces a regulated output voltage relative to the module's potential ground. The proposed regulator has a modular structure. Each regulator module consists of a shunt regulation submodule followed by a low-dropout voltage regulation submodule and is designed to deliver a nominal output current of 10 mA. The regulator module's schematic is presented along with a theoretical study and stability analysis. A test chip was designed in the 0.18-CMOS technology containing one main shunt regulator composed of 126 modules, as well as two separate regulators each composed of one single module. The characterization measurements show a correct dc startup for various load conditions, as expected by simulations. The output voltage of a single module is regulated with a precision <1%. Moreover, the regulator module works with a low voltage dropout of 200 mV for a large range of input current from 3 to 18 mA. The equivalent series resistance of a 40-module regulator is measured to be 15 including the wire bonding and test bench parasitics. The test chip is successfully tested in the serial mode and in the parallel mode. In the latter mode, the current mismatch between the parallel chips is measured to be less than 3.4% for an input current of 1 A. Moreover, transient measurements performed with an active load show proper functioning with no undershoots or overshoots. Finally, the test chip was irradiated with an X-ray source up to 125 Mrad. Measurements show a stable response of the regulator with an intrinsic output voltage variation of less than 1%.
机译:并联稳压器的设计符合CMOS像素检测器模块的串行供电要求,并与ATLAS检测器的下一次升级兼容。与并行供电方案相比,串行供电大大提高了系统的电源效率,并大大节省了电源电缆中的材料预算。在这种方案中,每个像素检测器芯片由并联稳压器供电,该并联稳压器吸收恒定电流并产生相对于模块电位接地的稳定输出电压。提出的调节器具有模块化结构。每个稳压器模块均由并联稳压子模块和低压差稳压子模块组成,旨在提供10 mA的额定输出电流。给出了调节器模块的原理图以及理论研究和稳定性分析。采用0.18-CMOS技术设计的测试芯片包含一个由126个模块组成的主并联稳压器,以及两个分别由一个模块组成的独立稳压器。正如仿真所预期的,特性测量结果显示了各种负载条件下的正确直流启动。单个模块的输出电压以<1%的精度进行调节。此外,调节器模块在200mV的低压差下工作,适用于3至18 mA的大范围输入电流。测得的40模块稳压器的等效串联电阻为15,包括引线键合和测试台寄生效应。测试芯片已在串行模式和并行模式下成功测试。在后一种模式下,对于1 A的输入电流,并行芯片之间的电流失配小于3.4%。此外,在有功负载下进行的瞬态测量显示出正常的功能,没有下冲或过冲。最后,用最高125 Mrad的X射线源照射测试芯片。测量结果表明,稳压器具有稳定的响应,其固有输出电压变化小于1%。

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