Analysis and Design of a Chip Filter With Low Insertion Loss and Two Adjustable Transmission Zeros Using 0.18- CMOS Technology

摘要

This paper presents the structure of a high-selectivity bandpass filter that is fabricated on low-resistivity silicon substrate with a commercial CMOS technology. The filter is constructed using crossed coplanar waveguide (CPW) lines and metal–insulator–metal capacitors to ensure that it has the desired passband characteristics. An adjustable capacitor between the input and output ports is employed to form a capacitive cross-coupled path, yielding two transmission zeros in the lower and upper stopbands, respectively. Additionally, the coupling mechanism can be modified by turning on or off the gate of an nMOS transistor to adjust the positions of the transmission zeros by applying an externally controlled voltage. To obtain a low passband loss and to minimize the chip size, high-impedance CPW transmission lines are adopted. Our analysis indicates that the CPW line possesses more advantages than the preferred stacked-ground CPW line for constructing the proposed filter. A very compact $X$ -band experimental prototype with a size of ${hbox{0.88}}times {hbox{0.54}} {hbox{mm}}^{2}$ was designed and fabricated. The measurements reveal an insertion loss of less than 3.2 dB in the passband, which is from 10.6 to 12.7 GHz, and rejection levels greater than 35 dB at the designed frequencies of transmission zeros. Moreover, the lower and upper transmission zeros can be shifted from 5 to 6.5 GHz and from 18 to 21.4 GHz, respectively, by changing the controlled voltage.