A High-Speed Power Detector for $D$-Band Communication

摘要

A $D$-band power detector (PD) consisting of a four-way power divider and four identical active PD units is proposed, where four individual PD units are derived by the input signals having the same amplitude, but a 90 $^{circ}$ phase difference. The outputs of the PD units are combined, to suppress the first, second, and third harmonics due to phase cancellation. Consequently, the ripple at the output is minimized. The proposed PD is designed and manufactured in a 0.25- $mu{hbox {m}}$ InP DHBT technology, which is characterized by on-chip measurements with both a sinusoidal signal and a binary amplitude shift-keying modulated signal at a data rate up to 13 Gb/s over different carrier frequencies from 100 to 150 GHz. Measured bit error rate for a ${hbox{2}} ^{7} -{hbox{1}}$ pseudorandom binary sequence is less than ${hbox{10}} ^{-12}$ at the carrier frequency of 120 GHz, and less than ${hbox{1.7}},times {hbox{10}} ^{-5}$ at the carrier frequency of 150 GHz. In addition, the proposed PD achieves state-of-the-art power/energy efficiency, which exhibits the lowest energy per bit of 1.1 pJ/bit. Total dc power consumption of the PD is 15 mW.