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Frequency Interleaving IF Transmitter and Receiver for 240-GHz Communication in SiGe:C BiCMOS

机译:用于SiGe:C BiCMOS中240 GHz通信的频率交织IF发送器和接收器

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This article presents a fully integrated modular wideband frequency interleaving (FI) transmitter and receiver for high data rate communication applications. At the transmitter side, three independent in-phase and quadrature-phase (IQ) baseband channels are upconverted to different intermediate frequencies (IFs) and then interleaved. At the receiver side, the interleaved signals are downconverted and separated back to each independent channel. Single-ended inputs and outputs are utilized to reduce the pin count, for a more practical realization and higher potential toward future system scaling. Special design techniques are followed to minimize crosstalk and intermodulation products between the channels. All circuits are manufactured and measured in a 130-nm SiGe:C BiCMOS technology with f(T)/f(max) 300/500 GHz. The FI transmitter achieves a channel bandwidth of 2.5 GHz with less than 3-dB difference across different channels until 15-GHz IF. It consumes 560 mW from 2.5 and 3.3 V supplies and occupies a silicon area of 1.9 mm(2). The FI receiver achieves a baseband channel bandwidth of 2.5 GHz with a 1-dB difference between the channels until the same IF. It consumes 860 mW from 2.5 and 3.3 V supplies and has a chip area of 1.55 mm(2). The circuits are deployed in a communication experiment; first, in a back-to-back test with a direct cable connection, demonstrating a data rate of 15.6 Gb/s across the three IQ channels with a 16-QAM modulation scheme and a worst case transmitter-to-receiver error vector magnitude (EVM) of -18.6 dB. Then, a wireless experiment is performed with a 240-GHz front end with on-chip antenna, demonstrating a data rate of 7.8 Gb/s with QPSK modulation and a worst case EVM of -8.3 dB, across a wireless link of 15 cm. To the best of our knowledge, this is the first article that demonstrates a wireless transmission at sub-terahertz (sub-THz) carrier frequencies utilizing FI architectures.
机译:本文介绍了用于高数据速率通信应用的完全集成的模块化宽带频率交织(FI)发送器和接收器。在发射机侧,三个独立的同相和正交(IQ)基带通道被上变频为不同的中频(IF),然后进行交织。在接收器端,交错的信号被下变频并分离回每个独立的通道。利用单端输入和输出来减少引脚数,以实现更实际的实现并为将来的系统扩展提供更大的潜力。遵循特殊的设计技术,以最小化通道之间的串扰和互调产物。所有电路均采用f(T)/ f(max)300/500 GHz的130nm SiGe:C BiCMOS技术制造和测量。 FI发射机达到2.5 GHz的信道带宽,直到15 GHz IF为止,不同信道之间的差异小于3 dB。它在2.5 V和3.3 V电源下的功耗为560 mW,占硅面积为1.9 mm(2)。 FI接收器实现了2.5 GHz的基带信道带宽,直到相同的IF为止,各信道之间存在1-dB的差异。它在2.5 V和3.3 V电源下的功耗为8​​60 mW,芯片面积为1.55 mm(2)。这些电路是在通信实验中部署的;首先,在直接电缆连接的背对背测试中,使用16-QAM调制方案和最差情况的发射机到接收机误差矢量幅度(3)来显示三个IQ通道上的数据速率为15.6 Gb / s( EVM)-18.6 dB。然后,使用带片上天线的240 GHz前端进行了无线实验,通过15 cm的无线链路证明了QPSK调制的数据速率为7.8 Gb / s,最差情况的EVM为-8.3 dB。据我们所知,这是第一篇文章,演示了利用FI架构以太赫兹(sub-THz)载波频率进行无线传输。

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