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首页> 外文期刊>IEEE Transactions on Microwave Theory and Techniques >An Injection-Locked Power Up-Converter in 65-nm CMOS for Cellular Applications
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An Injection-Locked Power Up-Converter in 65-nm CMOS for Cellular Applications

机译:用于蜂窝应用的65nm CMOS注入锁定功率上变频器

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摘要

This paper presents an injection-locked 65-nm CMOS circuit that upconverts and power amplifies baseband signals to RF. The circuit delivers an RF output power of 28.7 dBm, with a power gain and maximum power added efficiency (PAE) of 20.6 dB and 68.1%, respectively. Both AM-AM-conversion and AM-PM-conversion are low, less than 1 dB and 1 degrees, respectively, resulting in an EVM of 4.7% for Long Term Evolution (LTE) and 4.1% for WCDMA signals. The circuit provides an average output power of 20.3 dBm for LTE, with a PAE of 44.1%, and for WCDMA, the average output power is 23.8 dBm with a PAE of 55.6%. Supply modulation improves power back-off efficiency and the voltage range is from 540 mV to 3 V. The spectral mask for LTE signals has a worst case ACLR of 33.2 dBc using predistortion. For WCDMA signals, ACLR1 is 39.9 dBc and ACLR2 is 47.2 dBc, both values worst case and using baseband predistortion. This performance is achieved by introducing a cross-coupled cascode topology, and supporting theory and simulations are presented. The startup loop-gain and small-signal equivalents are derived, a power dissipation analysis is performed, and the injection circuit is analyzed to investigate the AM-PM behavior. Analysis and simulations show that, compared to conventional cascode amplifiers, PAE is improved by 24% (15% points). The circuit is implemented in an STM 65-nm CMOS process and occupies an area of 1.0 x 0.53 mm(2).
机译:本文提出了一种注入锁定的65 nm CMOS电路,该电路可以上变频并功率放大到RF的基带信号。该电路的射频输出功率为28.7 dBm,功率增益和最大功率附加效率(PAE)分别为20.6 dB和68.1%。 AM-AM转换和AM-PM转换都很低,分别小于1 dB和1度,因此长期演进(LTE)的EVM为4.7%,WCDMA信号的EVM为4.1%。该电路为LTE提供20.3 dBm的平均输出功率,而PAE为44.1%,而对于WCDMA,该平均输出功率为23.8 dBm,PAE为55.6%。电源调制可提高功率补偿效率,电压范围为540 mV至3V。LTE信号的频谱模板在使用预失真的情况下,最坏情况的ACLR为33.2 dBc。对于WCDMA信号,ACLR1为39.9 dBc,ACLR2为47.2 dBc,这两个值都是最差情况,并且使用基带预失真。通过引入交叉耦合的共源共栅拓扑来实现此性能,并给出了支持理论和仿真。得出启动环路增益和小信号等效值,进行功耗分析,并分析注入电路以研究AM-PM行为。分析和仿真表明,与传统的共源共栅放大器相比,PAE提高了24%(15%点)。该电路以STM 65-nm CMOS工艺实现,占地1.0 x 0.53 mm(2)。

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