Minimization of clock skew in VLSI circuits to within a tolerable range is important for dependable operation of any digital system. Moreover, excessive delay through a clock distribution network can significantly degrade the performance of the digital system. Differences in path lengths and active elements of a clock distribution network are largely responsible for clock skew while excessive delay is a result of very long signal routes in the network. Improved integrated circuit processes are placing an increasing demand on current clock routing schemes through higher clock rates and larger die sizes. This paper proposes a clock routing scheme that primarily minimizes clock skew in a general VLSI circuit whose functional elements may be of various sizes and placements. A secondary objective is to reduce the overall network delay. The clock distribution network is generated based on the analysis of RC trees. In the networks so generated, the delay seen from the clock entry point of a circuit to all modules within the circuit is nearly identical. In constructing the clock distribution networks, the fan out of a buffer is accounted for and flexibility in placement of buffers is utilized.
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