A Fast and High-Precision VCO Frequency Calibration Technique for Wideband $Delta Sigma $ Fractional-N Frequency Synthesizers

摘要

A VCO frequency calibration technique suitable for a wideband fractional-N PLL is presented. It provides a fast and high-precision search for an optimal discrete tuning curve of an $LC$ VCO during the coarse tuning process in a fractional-N PLL. A high-speed frequency error detector (FED) converts the VCO frequency to a digital value and computes the exact frequency difference from a target frequency. A minimum error code finder finds an optimal code that is closest to the target frequency. Due to the pure digital domain operation, a $Delta Sigma $ modulator in PLL can be deactivated during the calibration process, which makes this technique fast and accurate especially for a $Delta Sigma $ fractional-N PLL. We achieve a single-bit calibration time of only $kT_{REF}$ for obtaining a frequency resolution of $f_{REF}/k$, and compared to the conventional techniques, which is the best performance in terms of the calibration time versus resolution. Such fast VCO frequency calibration can greatly reduce the total lock time in a PLL. A 2.3–3.9 GHz fractional-N PLL employing the proposed calibration technique is implemented in 0.13 $~mu{hbox {m}}$ CMOS. Successful operation is verified through experimental results. The measured calibration time for a 6-bit capbank is 1.09 and 2.03$~mu{hbox {s}} $ for a frequency resolution of 19.2 and 4.8 MHz, respectively.