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A $Sigma Delta$-FIR-DAC for Multi-Bit $Sigma Delta$ Modulators

机译:用于多位$ Sigma Delta $调制器的$ Sigma Delta $ -FIR-DAC

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摘要

In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators ($Sigma Delta$Ms). This $Sigma Delta$ -finite-impulse-response-DAC ($Sigma Delta$-FIR-DAC) digitally converts the multi-bit output of the quantizer to a 1.5-bit signal at a higher rate and then injects it to the modulator loop filter by using a 1.5-bit DAC. An FIR filter is merged into 1.5-bit DAC to improve the clock jitter insensitivity. Furthermore, a new implementation of FIR-DAC is presented to reduce the output rate of $Sigma Delta$ -FIR-DAC down to the original rate of the modulator. This reduced rate $Sigma Delta$ -FIR-DAC (RR-$Sigma Delta$-FIR-DAC) can be used in both continuous-time and discrete-time $Sigma Delta$Ms. Theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators.
机译:本文针对多位连续时间sigma-delta调制器( $ Sigma Delta $ < / tex> 女士)。此 $ Sigma Delta $ -有限脉冲​​响应-DAC( $ Sigma Delta $ -FIR-DAC)将量化器的多位输出以较高的速率数字转换为1.5位信号,然后将其注入调制器环路滤波器通过使用1.5位DAC。 FIR滤波器被合并到1.5位DAC中,以改善时钟抖动的不敏感性。此外,提出了一种新的FIR-DAC实现,以降低 $ Sigma Delta $ -FIR-DAC的输出速率到调制器的原始速率。降低的比率 $ Sigma Delta $ -FIR-DAC(RR- $ Sigma Delta $ -FIR-DAC)可用于连续时间和离散时间 $ Sigma Delta $ 女士。仿真结果支持理论分析,以评估性能,时钟抖动抗扰性和针对所提出的调制器中DAC元件不匹配的鲁棒性。

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