A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers

摘要

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3(rd) order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.