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Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

机译:具有DTC的数模转换器:输出SFDR的理论分析

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摘要

In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave.
机译:在本文中,我们提出并分析了产生方波的脉冲输出数字频率转换器(DFC),该脉冲输出使用数字时间转换器(DTC)校正了输出频谱中的杂音(杂散)。我们专注于高级架构潜力,讨论适用于所建议系统的DTC的设计功能,并就输出频谱的清洁度探讨这种方法的可能性和局限性。行为模型仿真证实了所提出的理论分析。除了对输出杂散的分析描述之外,我们还得出了最坏情况杂散的闭式估计,这导致了一个简单的设计方程式。给定特定的无杂散动态范围(SFDR)目标,这对于确定DTC要求[位数和整数非线性(INL)]非常有用。我们显示出最大杂散强度(以dBc为单位)仅取决于输出频率与时钟频率之间的比率以及DTC功能(位数,INL和其他损伤),并随比率增加6 dB /倍频程。

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