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A quaternary partial-response class-IV transceiver for 125 Mbit/s data transmission over unshielded twisted-pair cables: principles of operation and VLSI realization

机译:用于通过非屏蔽双绞线电缆传输125 Mbit / s数据的四级部分响应IV类收发器:工作原理和VLSI实现

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The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of /spl plusmn/100 ppm. The implementation of all digital signal-processing functions in a single 0.5 /spl mu/m CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements.
机译:本文描述了一种实验收发器,该收发器用于通过普通语音级质量的非屏蔽双绞线电缆以125 Mbit / s的速率进行全双工传输,旨在用于光纤分布式数据接口(FDDI)网络。采用具有近端串扰(NEXT)消除和最大似然序列检测的四级部分响应IV类(QPRIV)全信道信令。 QPRIV信号的频谱形状有助于均衡并符合EMC法规。由于在FDDI系统中,每个发射器都可以独立计时,因此接收器必须应对要消除的NEXT信号与从远程发射器接收的信号之间的相位漂移。利用所选的收发器架构,发射器信号同步进行发射信号的数模转换,接收信号的模数转换以及自适应NEXT消除。从发射时序到受控接收时序的速率变化是通过自适应均衡器结合弹性缓冲区和偶尔的系数偏移来实现的。均衡器的调整速度足够快,以允许最大相位漂移为/ spl plusmn / 100 ppm。讨论了在单个0.5 / spl mu / m CMOS VLSI原型芯片中所有数字信号处理功能的实现。采用的标准单元设计导致6 W的功耗。通过高度重复的处理元件的定制设计,可以显着降低功耗。

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